?2010 fairchild semiconductor corporation 20a, 60v, 0.027 ohm, n-channel, logic level ultrafet? power mosfets packaging symbol features ? ultra low on-resistance - r ds(on) = 0.023 , v gs = 10v - r ds(on) = 0.027 , v gs = 5v ? simulation models - temperature compensated pspice? and saber? electriecal models - spice and saber thermal impedance models - www.fairchild.com ? peak current vs pulse width curve ? uis rating curve ? switching time vs r gs curves ordering information absolute maximum ratings t c = 25 o c, unless otherwise speci?ed this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ reliability data can be found at: http://www.mtp.fairchild.com/automotive.html. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certification. gate source drain (flange) d g s part number package brand note: when ordering, use the entire part number. add the suf?x t to obtain the variant in tape and reel, e.g., HUFA76429D3ST. units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 60 v drain to gate voltage (r gs = 20k ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 60 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain current continuous (t c = 25 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 25 o c, v gs = 10v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 4.5v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 20 20 20 20 figure 4 a a a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .uis figures 6, 17, 18 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 0.74 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief tb334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c notes: 1. t j = 25 o c to 150 o c. caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. HUFA76429D3ST_f085 ! ! jedec t o-252aa HUFA76429D3ST_f085 to-252aa 76429d data sheet september 2010 ? qualified to aec q101 ? rohs compliant HUFA76429D3ST_f085 rev. a HUFA76429D3ST_f085
electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 12) 60 - - v i d = 250 a, v gs = 0v , t c = -40 o c (figure 12) 55 - - v zero gate voltage drain current i dss v ds = 55v, v gs = 0v - - 1 a v ds = 50v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds(on) i d = 20a, v gs = 10v (figures 9, 10) - 0.0205 0.023 i d = 20a, v gs = 5v (figure 9) - 0.024 0.027 i d = 20a, v gs = 4.5v (figure 9) - 0.025 0.029 thermal specifications thermal resistance junction to case r jc to-251 and to-252 - - 1.36 o c/w thermal resistance junction to ambient r ja - - 100 o c/w switching specifications (v gs = 4.5v) turn-on time t on v dd = 30v, i d = 20a v gs = 4.5v, r gs = 7.5 (figures 15, 21, 22) - - 220 ns turn-on delay time t d(on) - 13 - ns rise time t r - 134 - ns turn-off delay time t d(off) - 30 - ns fall time t f - 55 - ns turn-off time t off - - 130 ns switching specifications (v gs = 10v) turn-on time t on v dd = 30v, i d = 20a v gs = 10v,r gs = 8.2 (figures 16, 21, 22) - - 65 ns turn-on delay time t d(on) - 7.7 - ns rise time t r - 36 - ns turn-off delay time t d(off) - 60 - ns fall time t f - 56 - ns turn-off time t off - - 175 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 10v v dd = 30v, i d = 20a, i g(ref) = 1.0ma (figures 14, 19, 20) - 38 46 nc gate charge at 5v q g(5) v gs = 0v to 5v - 21 25 nc threshold gate charge q g(th) v gs = 0v to 1v - 1.3 1.6 nc gate to source gate charge q gs - 3.8 - nc gate to drain "miller" charge q gd - 9.7 - nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 1480 - pf output capacitance c oss - 440 - pf reverse transfer capacitance c rss - 90 - pf sour ce to drain diode speci?cations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 20a - - 1.25 v i sd = 10a - - 1.00 v reverse recovery time t rr i sd = 20a, di sd /dt = 100a/ s - - 80 ns reverse recovered charge q rr i sd = 20a, di sd /dt = 100a/ s - - 230 nc HUFA76429D3ST! f0! ! ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
t ypical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t c , case temperature ( o c) po wer dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 25 15 20 50 75 100 125 150 0 25 i d , drain current (a) t c , case temperature ( o c) v gs = 4.5v v gs = 10v 175 5 10 0.1 1 2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 10 -5 t , rectangular pulse duration (s) z jc , normalized thermal impedance single pulse no tes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 100 600 10 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region t c = 25 o c i = i 25 175 - t c 150 for tempera tures above 25 o c dera te peak current as follo ws: v gs = 10v v gs = 5 _ ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a HUFA76429D3ST f0 85
figure 5. for ward bias safe operating area note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature typical p erf ormance curves (continued) 10 100 10 100 300 1 1 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) t c = 25 o c t j = max rated single pulse limited by r ds(on) area may be operation in this 10 100 0.01 0.1 1 10 i as , a valanche current (a) t av , time in avalanche (ms) star ting t j = 25 o c star ting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 50 0 10 20 30 40 1.5 2 2.5 3 3.5 4 i d, drain current (a) v gs , gate to source voltage (v) t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = -55 o c 50 0 10 20 30 40 0 1 2 3 4 i d , drain current (a) v ds , drain to source voltage (v) v gs = 3v v gs = 3.5v v gs = 5v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c v gs = 4v i d = 10a 10 20 30 40 2 4 6 8 10 v gs , ga te to source voltage (v) i d = 20a r ds(on) , drain to source on resistance (m ) pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 200 normalized drain t o source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 20a pulse duration = 80 s duty cycle = 0.5% max 160 ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
figure 11. normalized ga te threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance figure 16. switching time vs gate resistance typical p erf ormance curves (continued) 0.4 0.8 1.0 1.2 -80 -40 0 40 80 120 200 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold vol tage 0.6 160 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 200 t j , junction temperature ( o c) normalized drain t o source breakdown voltage i d = 250 a 160160 30 100 1000 3000 0.1 1.0 10 60 c, cap acitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 10 20 30 40 v gs , ga te to source voltage (v) v dd = 30v q g , ga te charge (nc) i d = 20a i d = 10a wa veforms in descending order: 5 15 25 35 100 200 400 0 1 0 20 30 40 50 0 switching time (ns) r gs , ga te to source resistance ( ) v gs = 4.5v, v dd = 30v, i d = 20a t r t f t d(on) t d(off) 300 100 200 300 0 1 0 20 30 40 50 0 switching time (ns) r gs , ga te to source resistance ( ) v gs = 10v, v dd = 30v, i d = 20a t d(off) t r t d(on) t f 50 150 250 ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
test cir cuits and waveforms figure 17. unclamped energy test circuit figure 18. unclamped energy waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform t p v gs 0.01 l i as + - v ds v dd r g dut var y t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(to t) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
pspice electrical model .subckt hufa76429d3 2 1 3 ; re v 5 july 1999 ca 12 8 2.03e-9 c b 15 14 2.03e-9 cin 6 8 1.39e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 68.10 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 5.42e-9 lsource 3 7 4.16e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 9.1e-3 rgate 9 20 2.80 rldrain 2 5 10 rlgate 1 9 54.2 rlsource 3 7 41.6 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 6.5e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*117),3))} .model dbodymod d (is = 1.25e-12 ikf = 10 rs = 8.40e-3 trs1 = 2.05e-3 trs2 = 3.85e-6 cjo = 1.68e-9 tt = 4.90e-8 m = 0.48 xti = 4.35) .model dbreakmod d (rs = 1.68e-1 trs1 = 1e-3 trs2 = -1e-6) .model dplcapmod d (cjo = 1.28e-9 is = 1e-30 n = 10 m = 0.8) .model mmedmod nmos (vto = 1.98 kp = 3.2 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 2.80) .model mstromod nmos (vto = 2.30 kp = 52 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.72 kp = 0.08 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 28.0 rs = 0.1) .model rbreakmod res (tc1 = 1.15e-3 tc2 = -5.40e-7) .model rdrainmod res (tc1 = 7.85e-3 tc2 = 1.95e-5) .model rslcmod res (tc1 = 4.97e-3 tc2 = 5.05e-6) .model rsourcemod res (tc1 = 1.5e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.85e-3 tc2 = -4.48e-6) .model rvtempmod res (tc1 = -1.92e-3 tc2 = 9.50e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -6.2 voff= -2.4) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.4 voff= -6.2) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -1.1 voff= 0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= -1.1) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vb at rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstr o drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rga te evtemp 9 esg lgate rlgate 20 + - + - + - 6 ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
saber electrical model rev 5 july 1999 t emplate hufa76429d3 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 1.25e-12, cjo = 1.68e-9, tt = 4.90e-8, xti = 4.35, m = 0.48) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.28e-9, is = 1e-30, n = 10, m = 0.8) m..model mmedmod = (type=_n, vto = 1.98, kp = 3.2, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.30, kp = 52, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.72, kp = 0.08, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.1, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.1) c.ca n12 n8 = 2.03e-9 c.cb n15 n14 = 2.03e-9 c.cin n6 n8 = 1.39e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.42e-9 l.lsource n3 n7 = 4.16e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -5.40e-7 res.rdbody n71 n5 = 8.40e-3, tc1 = 2.05e-3, tc2 = 3.85e-6 res.rdbreak n72 n5 = 1.68e-1, tc1 = 1.00e-3, tc2 = -1.00e-6 res.rdrain n50 n16 = 9.10e-3, tc1 = 7.85e-3, tc2 = 1.95e-5 res.rgate n9 n20 = 2.80 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 54.2 res.rlsource n3 n7 = 41.6 res.rslc1 n5 n51 = 1e-6, tc1 = 4.97e-3, tc2 = 5.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.5e-3, tc1 = 1.5e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.92e-3, tc2 = 9.50e-7 res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -4.48e-6 spe.ebreak n11 n7 n17 n18 = 68.10 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/117))** 3)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vb at rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstr o drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rga te evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
spice thermal model rev 26 july 1999 huf a76429d3 ctherm1 th 6 2.45e-3 ctherm2 6 5 8.15e-3 ctherm3 5 4 7.40e-3 ctherm4 4 3 7.45e-3 ctherm5 3 2 1.01e-2 ctherm6 2 tl 7.49e-2 rtherm1 th 6 9.00e-3 rtherm2 6 5 1.80e-2 rtherm3 5 4 9.15e-2 rtherm4 4 3 2.43e-1 rtherm5 3 2 3.50e-1 rtherm6 2 tl 3.62e-1 saber thermal model saber thermal model hufa76429d3 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.45e-3 ctherm.ctherm2 6 5 = 8.15e-3 ctherm.ctherm3 5 4 = 7.40e-3 ctherm.ctherm4 4 3 = 7.45e-3 ctherm.ctherm5 3 2 = 1.01e-2 ctherm.ctherm6 2 tl = 7.49e-2 rtherm.rtherm1 th 6 = 9.00e-3 rtherm.rtherm2 6 5 = 1.80e-2 rtherm.rtherm3 5 4 = 9.15e-2 rtherm.rtherm4 4 3 = 2.43e-1 rtherm.rtherm5 3 2 = 3.50e-1 rtherm.rtherm6 2 tl = 3.62e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case ?2010 fairchild semiconductor corporation HUFA76429D3ST_f085 rev. a huf a76429d3st _f085
? fairchild semiconductor corporation www.fairchildsemi.com trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. accupower ! auto-spm ! build it now ! coreplus ! corepower ! crossvolt ! ctl ! current transfer logic ! deuxpeed ? dual cool? e cospark ? efficientmax ! e sbc ! ? fairchild ? fairchild semiconductor ? fact quiet series ! f act ? fast ? fastvcore ! f etbench ! flashwriter ? * f ps ! f-pfs ! frfet ? global power resource sm green fps ! g reen fps ! e-series ! g max ! gto ! intellimax ! isoplanar ! megabuck ! microcoupler ! microfet ! micropak ! micropak2 ! millerdrive ! motionmax ! motion-spm ! optohit? optologic ? optoplanar ? ? pdp spm? p ower-spm ! powertrench ? powerxs? p rogrammable active droop ! qfet ? qs ! q uiet series ! rapidconfigure ! ! saving our world, 1mw/w/kw at a time? signalwise ! smartmax ! smart start ! spm ? stealth ! s uperfet ! supersot ! -3 supersot ! -6 supersot ! -8 supremos ! syncfet ! sync-lock? ? * t he power franchise ? tinyboost ! tinybuck ! tinycalc ! tinylogic ? tinyopto ! t inypower ! tinypwm ! tinywire ! trifault detect ! truecurrent ! * " serdes ! uhc ? ultra frfet ! u nifet ! vcx ! visualmax ! xs? * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. anti-counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support. counterfeiting of semiconductor parts is a growing problem in the industry. all manufacturers of semiconductor products are experiencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fairchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchild distributors are genuine parts, have full traceability, meet fairchild's quality standards for handling and storage and provide access to fairchild's full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unauthorized sources. fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions definition of terms datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. the datasheet is for reference information only. rev. i48
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